It has become increasingly desirable in the field of semiconductor device technology to provide bipolar and CMOS transistors on a single semiconductor substrate. Such a dual construction can provide high performance (better than CMOS transistors alone) without high power consumption (much lower than bipolar transistors alone). Similarly, it has become increasingly desirable to provide complementary NPN and PNP transistor pairs on a single semiconductor substrate because of the low power consumption of such a construction (lower than non-complementary construction).
As such, many efforts have been directed at producing bipolar and CMOS transistors on a single semiconductor substrate. Additionally, many efforts have been directed at producing complementary bipolar transistor pairs on a single semiconductor substrate. Generally, complementary bipolar transistor fabrication has included multiple polysilicon layers. This has created two main problems. First, the fabrication is expensive due to the multiple polysilicon layers utilized. Second, and for the same reason, the process cannot easily be integrated to include CMOS transistors.
Bipolar transistor (with or without CMOS) fabrication has included the process of photolithographically defining emitters and extrinsic bases, which process produces non-self-aligned emitters. Consequently, due to equipment inaccuracies, or alignment tolerances between layers, the relative locations of the non-self-aligned emitters and extrinsic bases cannot be precisely defined. To compensate for such reduced precision (non-self-alignment) the distance between the emitters and extrinsic bases must-be made sufficiently large as to prevent physical overlap. A lower performance device results from this design sizing requirement.
In response, prior art efforts have been directed at fabricating bipolar transistors with self-aligned emitters. One such bipolar transistor fabrication process, aimed at producing self-aligned emitters, utilizes multiple polysilicon layers and oxide layers to define emitters and extrinsic bases. The process includes defining a field oxide layer upon a substrate of silicon and thereafter defining recessed regions within the field oxide layer, one for the bipolar region, and one for the MOS region (if included). Thereafter, an intrinsic base region is formed within a recess in the bipolar region. Then a first polysilicon layer is deposited thereon with another oxide layer deposited on the polysilicon layer, and an opening is formed, for enabling subsequent formation of the emitter. Next, a further oxide layer is deposited thereon. Then a dry chemistry etching procedure is performed to remove the further oxide layer in the area where the emitter is to be performed. This leaves an insulating oxide layer on the polysilicon layer and oxide spacers on the side walls of the emitter opening. Thereafter, another polysilicon layer is deposited thereon and the emitter and extrinsic bases are formed. Such a fabrication process is disclosed in U.S. Pat. No. 4,868,135 to Ogura et al. A number of problems are associated with such a self-aligned bipolar transistor fabrication process. First, because of the dry etching procedure involved, the intrinsic base region surface can be damaged and the base width (distance between the bottom of the emitter and the bottom surface of the intrinsic base) cannot be controlled accurately. As such, low current leakage and poor parametric control may result. Second, performance is degraded when the base region is contacted above the field oxide layer due to the high resistance type polysilicon layers therebetween. In addition, due to the thin oxide layer between the two polysilicon layers, a large, unwanted base-to-collector capacitance results which is detrimental to the high speed performance. Finally, the emitter surface area must be made larger than the emitter contact area otherwise the emitter contact will overhang the emitter and short the transistor emitter and base. This emitter size constraint presents a serious drawback in terms of performance.
Accordingly, a general purpose of this invention is to provide a method of fabricating bipolar transistors and MOS transistors, including complementary transistors of either or both types, on a single semiconductor substrate with self-aligned emitters and a single polysilicon layer.